Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique

This article recommends a practical technique to design full chip (FC) clock tree of complex system-on-chip (SoC). In the new business environment, market prefers highly integrated but low power SoC with fast productivity and development cost. We observed that many techniques proposed in prior arts are no longer or enough. With that, we introduce flexible FC Clock network topology synthesis algorithm utilize hybrid meta-heuristic search for near optimum solution shorter turn-around time. Our work on 10nm product showed managed produce averagely 16.98% better global skew, 42.75% less divergence critical paths 64.5% balancing phase compared conventional ASIC methodology.